In creating a multiple layer (level) semiconductor devices on a semiconductor wafer, each layer making up the device may be subjected to one or more deposition processes, for example using chemical vapor deposition (CVD) or physical vapor deposition (PVD) and usually including one or more dry etching processes. A critical condition in semiconductor manufacturing is the absence of particulates on the wafer processing surface, since microscopic particles may interfere with and adversely affect subsequent processing steps leading to device degradation and ultimately semiconductor process wafer rejection.
While the wafer cleaning process has been always been a critical step in the semiconductor wafer manufacturing process, ultraclean wafers are becoming even more critical to device integrity. For example, as semiconductor feature sizes decrease, the detrimental affect of particulate contamination increases, requiring removal of ever smaller particles. For example, particles as small as 5 nm are no longer acceptable in many nano-integrated circuit manufacturing processes. To adequately meet requirements for ultraclean wafers in ULSI and VLSI the wafer surface must be essentially free of contaminating particles.
Processes that frequently result in particulate wafer contamination include plasma etching processes, for example a reactive ion etch (RIE) process including both anisotropic etching of dielectric insulating layers to form vias and metal etching of metal layers to form metal interconnect lines.
Typically, to reduce processing times and increase throughput, in prior at processes, ex-situ cleaning processes are performed following particle contaminating generating processes. For example, common particle removal mechanisms which may be exploited in the wet cleaning process, depending on the particle and the manner of adhesion to the wafer surface, including oxidizing degradation and dissolution and electrical repulsion between a particle and the wafer surface.
Standard wafer cleaning processes typically employ a dipping process whereby a plurality (batch) of process wafers are dipped sequentially in a series of solution baths. Following the chemical bath treatment a wafer rinse process is typically carried out, for example including wafer scrubbing by DI water. The scrubber utilizes a high-pressure spray of DI water with a retractable cleaning brush. Following the DI rinse process the process wafer is dried for example, using a solvent vapor drying process using a solvent such as isopropyl alcohol (IPA).
Vapor drying processes have been proposed in the prior art that utilize a solvent vapor to dry the semiconductor wafer following the deionized water rinse. Removal of substantially all of the water is critical for subsequent processes which may involve metal deposition processes to fill etched openings in a dielectric insulating layer. Typically low-K (low dielectric constant) inorganic materials are used in modern integrated circuit manufacturing where the low-K dielectric is composed of interconnecting porous material that readily absorbs water. Subsequent processes, including dielectric or metal deposition processes may be detrimentally affected by the presence of water, including causing inadequate adhesion of the overlying layer.
One solvent drying technique that has been used with some success makes use of the Marangoni effect. In this method, the substrate is withdrawn from the DI rinse water in a controlled manner while a solvent vapor stream is directed at the wafer above the air/rinse solution interface. In a Marangoni dryer, the drying principal is based on the different surface tension of IPA and DI water. The surface tension of the DI water is lowered by forming an azeotropic mixture of water and solvent, for example, isopropyl alcohol (IPA), which aids the removal by enhanced flow of water from the wafer surface as the wafer is withdrawn from the DI water bath.
One problem with prior art solvent vapor drying processes is that the efficiency of the drying process is frequently unpredictable due to variation is the concentration of solvent in the solvent vapor. For example, prior art vapor drying processes have limited temperature control capabilities where temperature variations can impact the steady state concentration of solvent vapor delivered to the wafer surface. In addition, prior art processes including prior temperature control have proved insufficient in maintaining a sufficiently high solvent vapor concentration during wafer drying including high aspect ratio semiconductor features. Temperature variations within the wafer drying space and along the vapor supply lines can result in inconsistent and inadequate solvent vapor concentrations. As a result, wafer yields are lowered as a result of defects caused by an incompletely dry wafer surface as well as requiring unnecessarily extended drying times to ensure complete wafer drying.
These and other shortcomings of the prior art are overcome by use of the solvent vapor drying method and apparatus described below.